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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad805* one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 world wide web site: http://www.analog.com fax: 617/326-8703 ? analog devices, inc., 1996 data retiming phase-locked loop clock recovery and data retiming application voltage controlled phase shifter phase detector loop filter retiming module vcxo (external) recovered clock ad805 data input gain retimed data product description the ad805 is a data retiming phase-locked loop designed for use with a voltage-controlled crystal oscillator (vcxo) to perform clock recovery and data retiming on nonreturn to zero (nrz) data. the circuit provides clock recovery and data retiming on standard telecommunications sts-3 or stm-1 data (155.52 mbps). a vectron c0-434y series vcxo circuit is used with the ad805 for specification purposes. similar circuit performance can be obtained using other commercially available vcxo circuits. the ad805-vcxo circuit used for clock recovery and data retiming can also be used for large factor frequency multiplication. the ad805-vcxo circuit meets or exceeds ccitt g.958 regenerator specifications for stm-i type a jitter tolerance and stm-1 type b jitter transfer. the simultaneous type a, wide- band jitter tolerance and type b, narrow-band jitter transfer allows the use of the ad805-vcxo circuit in a regenerative application to overcome optical line system interworking limit- ations based on signal retiming using type a passive tuned device technology such as surface-acoustic-wave (saw) or dielectric resonator filters, with type b active devices such as phase-locked loops (plls). the circuit vcxo provides a stable and accurate clock fre- quency signal with or without input data. the ad805 works with the vcxo to dynamically adjust the recovered clock fre- quency to the frequency associated with the input data. this frequency control loop tracks any low frequency component of jitter on the input data. since the circuit uses the vcxo for clock recovery, it has a high q for excellent wideband jitter at- tenuation. the jitter transfer characteristic of the circuit is with- in the jitter transfer requirements for a ccitt g.958 stm-1 type b regenerator, which has a corner frequency of 30 khz. the ad805 overcomes the higher frequency jitter tolerance limitations associated with traditional high q, pll based clock and data recovery circuits through the use of its data retiming loop. this loop, made up of the ad805s voltage-controlled features 155 mbps clock recovery and data retiming permits ccitt g.958 type a jitter tolerance permits ccitt g.958 type b jitter transfer random jitter: 0.6 8 rms pattern jitter: virtually eliminated jitter peaking: fundamentally none acquisition: 30 bit periods accepts nrz data without preamble single supply operation: C5.2 v or +5 v 10 kh ecl compatible phase shifter, phase detector, and loop filter, act to align input data phase errors to the stable recovered clock provided by the vcxo. the range of the voltage-controlled phase shifter, at least 2 unit intervals (ui), and the bandwidth of this loop, at roughly 3 mhz, provide the circuit with its wideband jitter tolerance characteristic. the circuit can acquire lock to input data very quickly, within 44 bit periods, due to the accuracy of the vcxo and the action of the data retiming loop. typical integrated second-order plls take at least several thousand bit periods to acquire lock. this is due to their having a wide tuning range vco. decreasing the loop damping of a traditional second-order pll shortens the length of the circuits acquisition time, but at the expense of greater jitter peaking. the ad805-vcxo circuit is a second- order pll that has no jitter peaking. the zero used to stabilize the control loop of the traditional second-order pll effects the closed-loop transfer function, causing jitter peaking in the jitter transfer function. in the ad805-vcxo circuit, the zero needed to stabilize the loop is implemented in the feedback path, in the voltage-controlled phase shifter. placing the zero in the feedback path results in fundamentally no jitter peaking since the zero is absent from the closed-loop transfer function. output jitter, determined primarily by the vcxo, is a very low 0.6 rms. jitter due to variations in input data density, pattern jitter, is virtually eliminated in the circuit due to the ad805s patented phase detector. the data retiming loop of the ad805 can be used with a passive tuned circuit (155.52 mhz) such as a bandpass or a saw filter for clock recovery and data retiming. the data retiming loop acts to servo the phase of the input data to the phase of the recovered clock from the passive tuned circuit in this type of application (see applications). the ad805 uses 10 kh ecl levels and consumes 375 mw from a +5 v or a C5.2 v supply. the device is specified for operation over the industrial temperature range of C40 c to +85 c and is available in a 20-pin plastic dip. * protected by u.s. patent no. 5,036,298 obsolete
C2C rev. 0 ad805Cspecifications AD805BN parameter condition min typ max units nominal data rate 1 155.52 mbps tracking range/capture range 1 50 70 ppm of nominal data rate static phase error 1 2 7 C1 prn sequence 7 33 degrees 2 23 C1 prn sequence 7 33 degrees output jitter 1 2 7 C1 prn sequence 0.6 1.0 degrees rms 2 23 C1 prn sequence 0.6 1.0 degrees rms jitter tolerance 1 f = 10 hz 375 440 unit intervals p-p f = 30 hz 125 147 unit intervals p-p f = 300 hz 12.5 16 unit intervals p-p f = 6.5 khz 2.2 3.2 unit intervals p-p f = 65 khz 2.2 3.0 unit intervals p-p f = 650 khz 0.84 1.4 unit intervals p-p f = 1.3 mhz 0.65 0.85 unit intervals p-p jitter transfer 1 2 7 C1 prn sequence peaking 0 0.1 2 db bandwidth 10 khz recovered clock skew t rcs 0.2 0.6 1.1 ns transitionless data run 1 1000 500 bit periods acquisition time 2 7 C1 prn sequence 30 44 bit periods vcxo control output resistance 1000 w vcxo control voltage high level (v cc C v oh ) no load 1 1.3 volts vcxo control voltage low level (v ol C v ee ) no load 0.8 1.15 volts power supply voltage (v min to v max ) C4.5 C5.2 C5.5 volts current t a = +25 c, v ee = C5.2 v 70 90 ma 95 ma input voltage levels t a = +25 c input logic high, v ih C1.08 C0.72 volts input logic low, v il C1.95 C1.59 volts output voltage levels t a = +25 c output logic high, v oh C1.08 C0.72 volts output logic low, v ol C1.95 C1.60 volts input current levels t a = +25 c input logic high, i ih 125 m a input logic low, i il 80 m a output slew times t a = +25 c rise time (t r ) 20%C80% 0.75 1.5 ns fall time (t f ) 80%C20% 0.75 1.5 ns buffered clock distortion (duty cycle distortion) r = 1/2, t a = +25 c, recovered clock output v ee = C5.2 v 0.5 % operating temperature range 1 (t min to t max ) C40 +85 c vcxo circuit specifications parameter condition min typ max units center frequency 155.52 mhz control voltage C4 C1 volts vcxo tuning range 50 70 ppm of center frequency modulation bandwidth 100 500 khz transfer function positive, monotonic n/a notes 1 these specifications reflect the performance of the circuit shown in figure 12. vcxo circuit parameters critical to overall circuit performance are listed above. 2 this specification results from tests accurate to 0.1 db, and from statistical analysis of the test results distribution. the ad805-vcxo circuit has no jitter peaking. reference the discussion in the theory of operation section. specifications subject to change without notice. (v ee = v min to v max , t a = t min to t max ( unless otherwise noted) obsolete
C3C rev. 0 ad805 absolute maximum ratings* supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C6 v input voltage (pin 19 or 20 to v ee ) . . . . . . . . v ee to +300 mv storage temperature range . . . . . . . . . . . . C65 c to +150 c maximum junction temperature plastic dip package . . . . . . . . . . . . . . . . . . . . . . . . . . 150 c storage temperature range . . . . . . . . . . . . C65 c to +150 c lead temperature (soldering 60 sec) . . . . . . . . . . . . . +300 c *stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of the specification is not implied. exposure to an absolute maximum rating condition for an extended period may adversely affect device reliability. pin configuration notes: pin 6 and 18 are digital substrate and should be connected to pins 7 and 15 which are digital v ee . pin 10 is analog substrate and should be connected to pin 9, which is analog v ee . dataout clkout dataout v cc2 clkout subst v ee v cc1 av ee asubst clkin clkin subst datain datain v ee v cc1 av cc vcxo control nc 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 top view (not to scale) ad805 nc = no connect t rcs dataout 50% clkout 50% figure 1. recovered clock skew (see specifications page) pin descriptions number mnemonic description 1 dataout differential retimed data output 2 dataout differential retimed data output 3v cc2 digital ground 4 clkout differential recovered clock output 5 clkout differential recovered clock output 6 subst substrate 7v ee digital v ee 8v cc1 digital ground 9av ee analog v ee 10 asubst analog substrate 11 nc no connection 12 vcxo control vcxo control voltage output 13 av cc analog ground 14 v cc1 digital ground 15 v ee digital v ee 16 clkin differential clock input 17 clkin differential clock input 18 subst substrate 19 datain differential data input 20 datain differential data input ordering guide and thermal characteristics operating package device description temperature u ja option AD805BN 20-pin plastic dip C40 c to +85 c80 c/w n-20 warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad805 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. obsolete
ad805 C4C rev. 0 glossary ad805 performance is specified using a vectron c0-434y ecl series hybrid vcxo, scd no. 434y2365. nominal data rate this is the data rate that the circuit is specified to operate on. the data format is nonreturn to zero (nrz). operating temperature range (t min to t max ) this is the operating temperature range of the ad805 in the circuit. each of the additional components of the circuit is held at 25 c, nominal. the operating temperature range of the circuit can be extended to the operating temperature range of the ad805 through the selection of circuit components that operate from t min to t max . tracking range this is the range of input data rates over which the circuit will remain in lock. the vcxo control voltage range and the vcxo frequency range determine circuit tracking range. capture range this is the range of frequencies over which the circuit can acquire lock. the vcxo control voltage range and the vcxo frequency range determine circuit capture range. static phase error this is the steady-state phase difference, in degrees, between the recovered clock sampling edge and the optimum sampling instant, which is assumed to be halfway between the rising and falling edges of a data bit. gate delays between the signals that define static phase error and ic input and output signals prohibit direct measurement of static phase error. recovered clock skew, t rcs this is the time difference, in ns, between the recovered clock signal rising edge midpoint and midpoint of the rising or falling edge of the output data signal. refer to figure 1. data transition density, r this is a measure of the number of data transitions, from 0 to 1 and from 1 to 0, over many clock periods. r is the ratio (0 r 1) of data transitions to clock periods. transitionless data run this is measured by interrupting an input data pattern with r = 1/2 with a block of data bits without transitions, and then reapplying the r = 1/2 input data. the circuit will handle this sequence without making a bit error. the length of the block of input data without transitions that an ad805-vcxo circuit can handle is a function of the vcxo k 0 . the vcxo in the circuit of figure 12 has a k 0 of 60 radians/volt, nominally. jitter this is the dynamic displacement of digital signals from their long term average positions, measured in degrees rms, or unit intervals (ui). jitter on the input data can cause dynamic phase errors on the recovered clock. jitter on the recovered clock causes jitter on the retimed data. output jitter this is the jitter on the retimed data, in degrees rms, due to a specific pattern or some pseudo-random input data sequence (prn sequence). the random output jitter of the vcxo contributes to output jitter. jitter tolerance jitter tolerance is a measure of the circuits ability to track a jittery input data signal. jitter on the input data is best thought of as phase modulation and is usually specified in unit intervals (ui). the circuit will have a bit error rate less than 1 10 C10 when in lock and retiming input data that has the specified jitter applied to it. refer to the theory of operation section for a descrip- tion of the jitter tolerance of the ad805-vcxo circuit. jitter transfer the circuit exhibits a low-pass filter response to jitter applied to its input data. the circuit jitter transfer characteristics are measured using the method described in ccitt recommenda- tion g.958, geneva 1990, section 6.3.2. this method involves applying sinusoidal input jitter up to the jitter tolerance mask level for an stm-1 type a regenerator. bandwidth this describes the frequency at which the circuit attenuates sinusoidal input jitter by 3 db. peaking this describes the maximum jitter gain of the circuit in db. acquisition time this is the transient time, measured in bit periods, required for the circuit to lock on input data from its free-running state. buffered clock distortion this is a measure of the duty cycle distortion at the ad805 clkout signals relative to the duty cycle distortion at the ad805 clkin signals. bit error rate vs. signal-to-noise ratio the ad805 is intended to operate with standard ecl signal levels at the data input. although not recommended, smaller input signals are tolerable. figure 6 shows the bit error rate performance versus input signal-to-noise ratio for input signal amplitudes of full 900 mv ecl, and decreased amplitudes of 80 mv and 20 mv. wideband amplitude noise is summed with the data signals as shown in figure 2. the full ecl, 80 mv, and 20 mv input signals give virtually indistinguishable results. the axes used for figure 6 are scaled so that the theoretical bit error rate vs. signal to noise ratio curve appears as a straight line. the curve that fits the actual data points has a slope that matches the slope of the theoretical curve for all but the higher values of signal-to-noise ratio and lower values of bit error rate. for high values of signal-to-noise ratio, the noise generator used clips, and therefore is not true gaussian. the extreme peaks of the noise cause bit errors for high signal to noise ratios and low bit error rates. the clipping of the noise waveform limits bit errors in these cases. obsolete
ad805 C5C rev. 0 power splitter + + + power combiner power combiner differential signal source circuit under test datain datain 0.47 m f 0.47 m f 50 w 50 w 75 w 180 w 1.0 m f filter noise source gnd ?.2 v ? ? figure 2. bit error rate vs. signal-to-noise ratio test: block diagram 0 ?0 ?0 1 10 1000 100 ?5 ? jitter frequency ?khz jitter gain ?db 1.3 ui input jitter 0.3 ui input jitter type a mask input jitter ccitt type b mask figure 3. jitter transfer C bandwidth ? ? 110 ? jitter frequency ?khz jitter gain ?db 1.3 ui input jitter 0.3 ui input jitter ccitt type a mask input jitter figure 4. jitter transfer C peaking 100 1 0.1 1 1000 100 10 0.1 10 frequency ?khz jitter tolerance ?uip-p ccitt type a mask figure 5. jitter tolerance e-1 e-2 e-15 89 21 20 19 18 17 16 15 14 13 11 10 12 3 4 5 6 8 10 12 5e-2 3e-2 2e-2 5e-3 3e-3 2e-3 5e-4 3e-4 2e-4 22 23 24 s/n ?db 80mv ecl 20mv bit error rate figure 6. bit error rate vs. signal-to-noise ratio 0 400 1.5 0.5 C200 1.0 2.0 200 0 i out C m a v cc C v oh v ol C v ee vcxo control voltage C volts i out v cc v ee = C5.2v ad805 figure 7. vcxo control voltage vs. load obsolete
ad805 C6C rev. 0 theory of operation the ad805 is a delay- and phase- locked loop circuit for clock recovery and data retiming from an nrz-encoded data stream. figure 8 is a block diagram of the device shown with an external vcxo. the ad805-vcxo circuit tracks the phase of the input data using two feedback loops that share a common control voltage. a high speed delay-locked loop path uses an on-chip voltage-controlled phase shifter (vcps) to track the high frequency components of jitter on the input data. a separate frequency control loop, using the external vcxo, tracks the low frequency components of jitter on the input data. voltage controlled phase shifter phase detector loop filter retiming module vcxo (external) recovered clock ad805 data input internal loop control voltage vcxo control voltage retimed data figure 8. ad805-vcxo clock recovery block diagram the two loops work together to null out phase error. for example, when the clock is behind the data, the phase detector drives the vcxo to a higher frequency and also increases the delay through the vcps. these actions serve to reduce the phase error. the faster clock picks up phase while the delayed data loses phase. when considering a static phase error, it is easy to see that since the control voltage is developed by a loop integrator, the phase error will eventually reduce to zero. another view of the circuit is that the ad805 vcps implements the zero that is required to stabilize a second order phase-locked loop and that the zero is placed in the feedback path so it does not appear in the closed-loop transfer function. jitter peaking in an ordinary second order phase-locked loop is caused by the presence of this zero in the closed-loop transfer function. since the ad805-vcxo circuit is free of any zero in its closed-loop transfer function, the circuit is free of jitter peaking. a linearized block diagram of the ad805-vcxo circuit is shown in figure 9. the two loops simultaneously provide wide- band jitter accommodation and narrow-band jitter filtering. ? x phase shifter + + k int vco 1 s z e t y phase detector ? 1 s z(s) x(s) 1 s 2 k + t s + 1 = e(s) x(s) s 2 s 2 + k t s + k = figure 9. ad805-vcxo circuit linearized block diagram the jitter transfer function, z(s)/x(s), is second order and low pass, providing excellent filtering. note that the jitter transfer function has no zero, unlike ordinary second-order phase-locked loops. this means that the circuit has fundamentally no jitter peaking (see figure 10). having no jitter peaking makes this circuit ideal for signal regeneration applications where jitter peaking in any regenerative stage can contribute to hazardous jitter accumulation. (db) jitter out jitter in 0 db ordinary pll y(s) x(s) s low s high log w 1 t z(s) x(s) ad805 ?vcxo figure 10. circuit jitter transfer functions the error transfer function, e(s)/x(s), has the same high pass form as an ordinary phase-locked loop. this transfer function is free to be optimized to give excellent wide-band jitter accommo- dation since the jitter transfer function, z(s)/x(s), provides the narrow-band jitter filtering. the circuit has an error transfer bandwidth of 3 mhz and a jitter transfer bandwidth of 10 khz. the circuits two loops contribute to overall jitter accommoda- tion. at low frequencies, the integrator provides high gain so that large jitter amplitudes can be tracked with small phase errors between inputs of the phase detector. in this case, the vcxo is frequency modulated and jitter is tracked as in an ordinary phase-locked loop. the amount of low frequency jitter that can be tracked is a function of the vcxo tuning range. a wider tuning range corresponds to increased accommodation of low frequency jitter. the internal loop control voltage remains small for small phase errors, so the vcps remains close to the center of its range, contributing little to jitter accommodation. at medium jitter frequencies, the gain and tuning range of the vcxo are not enough to track input jitter. in this case the vcxo control voltage input starts to hit the rails of its maxi- mum voltage swing and the vcxo frequency output spends most of the time at one or the other extreme of its tuning range. the size of the vcxo tuning range therefore has a small effect on the jitter accommodation. the ad805 internal loop control voltage is now larger, so the vcps takes on the burden of tracking input jitter. the vcps range (in ui) is seen as the plateau on the jitter tolerance curve (figure 11). the vcps has a minimum range of 2 ui. 100 10 0.1 0.1 1 10000 1000 100 10 1 frequency ?khz jitter tolerance ?uip-p ad805-vcxo jitter tolerance ccitt type a mask figure 11. jitter accommodation design limit obsolete
ad805 C7C rev. 0 the gain of the loop integrator is small for high jitter frequen- cies, so that larger phase differences between the phase detector inputs are needed to make the internal loop control voltage big enough to tune the range of the vcps. large phase errors at high jitter frequencies cannot be tolerated. in this region, the gain of the loop integrator determines the jitter accommodation. since the gain of the loop integrator declines linearly with frequency, jitter accommodation decreases with increasing jitter frequency. at the highest frequencies, the loop gain is very small and little tuning of the vcps can be expected. in this case, jitter accommodation is determined by the eye opening of the input data, the static phase error and the residual loop jitter. the jitter accommodation is roughly 0.5 ui in this region. the corner frequency between the declining slope and the flat region is the 3 mhz closed-loop bandwidth of the ad805s internal delay-locked loop. using the ad805 ground planes use of two ground planes, an analog ground plane and a digital ground plane, is recommended. this will isolate noise that may be on the digital ground plane from the analog ground plane. power supply connections power supply decoupling should take place as close to the ic as possible. this will keep noise that may be on a power supply from affecting circuit performance. use of a 10 m f tantalum capacitor between v ee and ground is recommended. use of 0.1 m f ceramic capacitors between ic power supply or substrate pins and either analog or digital ground is recom- mended. refer to schematic, figure 12, for advised connections. the ceramic capacitors should be placed as close to the ic pins as possible. connections from v ee to load resistors for datain, dataout, clkin, and clkout signals should be individual, not daisy chained. this will avoid crosstalk on these signals. transmission lines use of 50 w transmission lines are recommended for datain, dataout, clkin, and clkout signals. terminations termination resistors should be used for datain, clkin, dataout, and clkout signals. metal, thick film, 1% tolerance resistors are recommended. termination resistors for the datain and clkin signals should be placed as close as possible to the datain and clkin pins. input buffer use of an input buffer, such as a 10h116 line receiver ic, is suggested for an application where the datain signals do not come directly from an ecl gate, or where noise immunity on the datain signals is an issue. applications 155.52 mbps clock recovery and data retiming using at&t 157-type vhf voltage-controlled crystal oscillator the ad805 design can be used with any vcxo circuit that has a gain of roughly 1 3 10 6 rad/volt-sec, a frequency pull range of at least 50 ppm, a positive slope (a greater vcxo control voltage corre sponds to a greater output frequency) and a modulation bandwidth of 500 khz. these vcxo parameters contribute to overall circuit low frequency jitter tolerance and jitter transfer. the output jitter of the overall circuit is largely determined by the output jitter of the vcxo. the ad805 adds little jitter since it just buffers the vcxo frequency output, adding distortion (duty cycle distortion) of only 0.5%. overall circuit jitter bandwidth is determined by the slope of the vcxo output frequency vs. control voltage curve. a greater slope corresponds to a greater jitter bandwidth. figure 12 shows a schematic of the ad805 in a 155.52 mbps clock recovery and data retiming application with an at&t 157-type vcxo (see insert). figures 15 and 16 show typical jitter tolerance and jitter transfer curves for the circuit. note that the 157-type vcxo control voltage bandwidth (modulation bandwidth) varies with respect to control voltage from 80 khz to 500 khz. the low value of this modulation bandwidth causes some jitter peaking when used with the ad805. the limited modulation bandwidth introduces excess phase in the frequency control loop through the vcxo. this causes the frequency control loop to become less damped. jitter peaking of 1 db or 2 db results in the jitter transfer function. the compens ation network on the vcxo control voltage between the ad805 and the 157-type vcxo shown in figure 12, effectively reduces the high frequency loop gain through the frequency control loop. the addition of this compensation network eliminates jitter peaking. the compensation network 1 k w resistor works with the ad805 vcxo control 1 k w output impedance to halve the loop crossover frequency. this avoids excess phase caused by the limited modulation band- width of the 157-type vcxo. obsolete
ad805 C8C rev. 0 dataout 1 datain 0.1 m f digital ground analog ground ?.2v ?.2v ?.2v r5 100 w r6 100 w dataout dataout r7 100 w r8 100 w r3 100 w clockout clockout j1 j4 r1 100 w r2 100 w r4 100 w r10 154 w r9 154 w r11 154 w r12 154 w ?.2v c2 10 m f c3 0.1 m f c4 0.1 m f c5 0.1 m f c6 0.1 m f c8 r15 130 w r16 130 w r13 80.6 w r14 80.6 w 1 r19 130 w r20 130 w c11 0.1 m f ?.2v r17 80.6 w r18 80.6 w ?.2v c10 0.1 m f z2 10h116 j5 ?.2v datain datain ?.2v c7 0.1 m f ?.2v vectron co-434v vcxo ?.2v c12 0.1 m f r21 130 w r22 130 w r23 80.6 w r24 80.6 w ?.2v c16 0.1 m f dataout v cc2 clkout clkout subst v ee v cc1 av ee asubst 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 datain subst clkin clkin v ee v cc1 av cc vcxo control nc 2 3 4 5 6 7 8 nc = no connect j2 j3 c9 0.1 m f 16 15 14 13 12 11 10 9 9 10 16 8 j6 z3 at&t 157-type vcxo 1 2 16 15 3 14 4 13 5 12 6 11 7 10 8 9 r25 1k w c1 1.0 m f ?.2v c13 0.1 m f 6 a b c c b a 157 at&t type vcxo circuit 20mh 1nf optional notch filter * * a notch filter may be used to filter a vcxo circuit's spurious response effectively. ad805 z1 figure 12. evaluation board schematic, negative supply figure 13. evaluation board, component side figure 14. evaluation board, solder side obsolete
ad805 C9C rev. 0 table i. evaluation board, negative supply: components list reference designator description quantity r1C8 resistor, 100 w , 1% 8 r9C12 resistor, 154 w , 1% 4 r13, 14, 17, 18, 23, 24 resistor, 80.6 w , 1% 6 r15, 16, 19C22 resistor, 130 w , 1% 6 c2 10 m f, tantalum 1 c3C12, c15 0.1 m f, ceramic chip 11 z1 ad805 1 z2 10h116, ecl line receiver 1 vectron co-434y vcxo 1 z3 at&t 157-type vcxo 1 100 1 0.1 1 1000 100 10 0.1 10 jitter frequency ?khz jitter tolerance ?uip-p ccitt type a mask vectron at&t figure 15. ad805-vcxo circuit jitter tolerance 0 ?0 ?0 1 10 1000 100 ?5 ? jitter frequency ?khz jitter gain ?db vectron 1.3 ui input jitter at&t 1.3 ui input jitter ccitt type b mask figure 16. ad805-vcxo circuit jitter transfer 155.52 mbps clock recovery and data retiming using a surface acoustic wave (saw) filter the ad805 can be used with a 155.52 mhz saw filter circuit for clock recovery and data retiming. in this type of application (refer to figure 17), the saw filter circuit is used to generate a 155.52 mhz clock from the input data. the ad805 data retiming loop formed by the voltage-controlled phase shifter, the phase detector and the loop filter, act to servo the phase of the input data to the phase of the recovered clock. the ad805 can compensate up to 180 phase variance through the saw filter circuit. the ad805 replaces the d flip-flop and phase shifter components found in traditional saw filter-based clock recovery and data retiming circuits. use of the ad805 eliminates the phase shifter to saw filter matching needed to get traditional saw filter-based circuits to perform over operating conditions. the jitter bandwidth and the output jitter of the overall circuit is determined largely by the saw filter used. the ad805 retimes the input data to the recovered clock and buffers the recovered clock from the saw filter circuit. the ad805 plays a role in the jitter accommodation of the overall circuit. the ad805s phase shifter range and the bandwidth of the data retiming loop provide for at least 2 ui p-p jitter tolerance to 1 mhz. the length of a transitionless block of data that will not cause the circuit to lose lock or start making bit errors is determined by the q of the saw filter used. figure 17 shows a schematic of the ad805 used with a toyocom tqs-610j-6r saw filter. the circuit that precedes the saw filter feeds the filter with a pulse at each data transi- tion. the line receiver circuit that immediately follows the saw filter provides gain to the saw filter output to drive the ad805 clkin signals. obsolete
ad805 C10C rev. 0 dataout 1 datain 0.1 m f digital ground analog ground ?.2v ?.2v ?.2v r5 100 w r6 100 w dataout dataout r7 100 w r8 100 w r3 100 w clockout clockout j1 j4 r1 100 w r2 100 w r4 100 w r10 154 w r9 154 w r11 154 w r12 154 w ?.2v c2 10 m f c3 0.1 m f c4 0.1 m f c5 0.1 w c6 0.1 m f c8 r15 130 w r16 130 w r13 80.6 w r14 80.6 w 1 r19 130 w r20 130 w ?.2v r17 80.6 w r18 80.6 w c10 0.1 m f z2 10h116 j5 ?.2v datain datain ?.2v c7 0.1 m f ?.2v ?.2v c12 0.1 m f r35 130 w r34 130 w dataout v cc2 clkout clkout subst v ee v cc1 av ee asubst 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 datain subst clkin clkin v ee v cc1 av cc vcxo control nc 2 3 4 5 6 7 8 nc = no connect j2 j3 c9 0.1 m f 16 15 14 13 12 11 10 9 c11 0.1 m f j6 r33 80.6 w r32 80.6 w r 80.6 w r30 10k w r31 10k w c21 0.47 m f r28 10k w r29 10k w c20 0.47 m f c19 0.47 m f 7 6 10 9 15 14 13 12 8 16 3 2 5 4 1 r26 274 w r27 274 w c17 0.1 m f r24 274 w r25 274 w c16 0.1 m f ?.2v ?.2v c10 0.1 m f c15 1nf c14 1nf r23 590 w 1/3 z3 10h116 toyocom tqs-610j-6r r22 590 w c13 0.1 m f r21 226 w l1 1 m h t50-10 core, 18 turns ?.2v 1/3 z3 1/3 z3 ad805 z1 figure 17. ad805-saw filter clock recovery and data retiming circuit schematic table ii. ad805-saw filter clock recovery and data retiming components list reference designator description quantity r1Cr8 resistor, 100 w , 1% 8 r9Cr12 resistor, 154 w , 1% 4 r13, r14, r17, r18, r32, r33 resistor, 80.6 w , 1% 6 r15, r16, r19, r20, r34, r35 resistor, 130 w , 1% 6 r21 resistor, 226 w , 1% 1 r22, r23 resistor, 590 w , 1% 2 r24Cr27 resistor, 274 w , 1% 4 r28Cr31 resistor, 10 k w , 1% 4 c2 10 m f, tantalum 1 c3Cc13, c16Cc18 0.1 m f, ceramic chip 14 c14, c15 1 nf 2 c19Cc21 0.47 mf 3 l1 1 m h, t50-10 core, 18 turns, 1 micrometals, inc. z1 ad805 1 z2, z3 1oh116, ecl line receiver 2 z4 toyocom tqs-610j-6r saw 1 obsolete
ad805 C11C rev. 0 large factor frequency multiplication to 155.52 mhz the ad805-vcxo combination can be used to multiply a frequency at the ad805s datain by a large integer multiple. this is useful for generating a 155.52 mhz bit clock from a 19.44 mhz byte clock (multiplication factor of 8). the highly accurate center frequency of the vcxo makes even larger factor frequency multiplication possible. the vcxo will not lock on a false harmonic even for large multiplication factors. for example, a vcxo with center frequency accuracy of 100 ppm will allow frequency multiplication by a factor as large as 5000. this is because the 5000th harmonic of 31.104 khz is 155.52 mhz, and the 4999th and the 5001st harmonics are 200 ppm away from the vcxo center frequency. since the accuracy and tuning range of the vcxo constrain its output frequency to within 100 ppm of center frequency, the circuit will reliably pick the 5000th harmonic. frequency multiplication by an odd factor is possible using the ad805-vcxo combination. this is not obvious. consider a 51.84 mhz input multiplied by a factor of 3 to get to 155.52 mhz. in this case, the edge spacing of the 51.84 mhz signal is 9.65 ns, or 1-1/2 periods of the expected 155.52 mhz output. in theory, every other edge of the 51.84 mhz at the ad805s datain is inte rpreted as 180 out of phase. in practice, however, the inherent loop jitter dithers these edges to give +179 then C179 out of phase measurements on alternate edges. measurements on these alternate edges cancel. the circuit phase locks to the other set of alternate edges. the very low gain of the vcxo and the narrow bandwidth of the jitter transfer function gives an output that has low jitter even though alternate input edges are out of phase. when multiplying by a factor of 3, the dataout will have a repeating 110 or 100 pattern. either pattern can occur since either the rising or falling edges of the 51.84 mhz signal at the datain can be the out of phase set of alternate edges. figure 18 shows the output jitter performance of an ad805- vcxo circuit for different integer frequency multiplication factors. 60 0 10 100 input clock frequency ?mhz output jitter ?ps rms 50 40 30 20 10 figure 19. ad805-vcxo circuit clock output jitter vs. integer multiplier deskewing isochronous 155.52 mbps data streams the ad805 can be used for deskewing a 155.52 mbps data stream to a reference 155.52 mhz clock when the clock is isochronous with the data. figure 19 shows a diagram of an ad805 in a deskewing application. the data input to the ad802-155 clock recovery circuit and the data input to the ad805 were generated using the same 155.52 mhz clock. the ad805 data retiming loop formed by the voltage-controlled phase shifter, the phase detector, and the loop filter act to align the phase of the input data to the phase of the recovered clock. this eliminates skew that can exist between two isochronous data paths. the ad805 will track 180 change in skew after initial locking without bit errors. if the skew changes by more than 180 after lock, it is possible to exceed the range of the voltage controlled phase shifter. exceeding the phase shifter range will force the ad805 data retiming loop to reacquire to the center of the phase shifter. during this reacquisition, it is possible to make 3000 bit errors. phase detector recovered clock compensating zero c d vco retiming module frac output ad802-155 voltage controlled phase shifter buffered clock ad805 gain reference data input data input vcxo control output ? frequency detector retiming module loop filter retimed data phase detector loop filter retimed data figure 19. ad805 deskewing circuit diagram obsolete
ad805 C12C rev. 0 outline dimensions dimensions shown in inches and (mm). c1777C10C4/93 printed in u.s.a. 20-pin plastic dual in-line package (n-20) 20 110 11 1.060 (26.90) 0.925 (23.50) 0.280 (7.11) 0.240 (6.10) pin 1 seating plane 0.022 (0.558) 0.014 (0.356) 0.210 (5.33) max 0.130 (3.30) min 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.160 (4.06) 0.115 (2.93) 0.060 (1.52) 0.015 (0.38) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) obsolete

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